The present invention relates to a semiconductor device, and more particularly, to a semiconductor device isolation layer that can prevent defects from occurring in a single SOD (spin-on dielectric) process and a method for forming the same.
As the design for a semiconductor device has decreased, the aspect ratio of trenches of the semiconductor device has increased. As a result, a very fluid insulation material, such as an SOD material, has been used as a material for filling the trenches. For example, PSZ (polysilazane) can be used as the SOD material for forming an isolation layer. PSZ is formed by an Si—N bonding structure and an oxidation reaction must occur after PSZ is applied.
If the oxidation reaction occurs at a low temperature, it is difficult to control the process since a wet etch rate increases excessively in a subsequent wet cleaning process causing a problem. On the contrary, if the oxidation reaction occurs at a high temperature, byproducts such as NH3, SiH4 and H2 are not discharged, but rather coalesce in a layer since the oxidation reaction occurs too quickly causing yet another problem.
In particular, defects in the form of pores are produced by the byproducts coalescing in a layer. During a subsequent wet cleaning process, the pores develop into voids in an isolation layer. The voids can adversely influence a subsequent gate process and can cause bridges between gates and landing plug contacts.
To cope with these problems according to the conventional art, the SOD material is removed to a predetermined depth of the trench through wet etching after filling each trench with the SOD material. A mechanically stable oxide layer, such as an HDP (high density plasma) oxide layer or a USG (undoped silicate glass) oxide layer, is subsequently filled in the trench where the SOD material was partially removed. In this way, an isolation layer having a bilayer structure is formed.
However, as the size of a semiconductor device shrinks below a 50 nm level, the method for forming an isolation layer with a bilayer structure cannot be properly performed because the trench aspect ratio abruptly increases as the semiconductor device shrinks.